1. Field of the Invention
The present invention relates to a semiconductor device in which MPU and DRAM as a secondary cache memory are mounted on the same chip.
2. Description of the Related Art
Conventionally, SRAM (Static Random Access Memory) is used as a secondary cache memory of MPU (Micro Processing Unit) of a large computer. This is because the SRAM which is easy to realize a high speed is suitable for a cache memory requiring a high speed of access.
Some MPU for a cheap computer may have a small capacity of a secondary cache memory on the same chip as the MPU. However, in order to realize a capacity (more than 1 Megabyte) required by a MPU of a large computer, it is an actual solution to connect the MPU to a synchronous SRAM on a module, if considering a chip size and a cost.
Recently, it is not seldom that the MPU is used as a module (MPU module) in which the MPU and the SRAM for the secondary cache memory are mounted on a single printed circuit board. This MPU module is directly manufactured by an LSI maker manufacturing the MPU. The merit is as follows. Since the operation of a high speed is performed between the MPU and the SRAM for the secondary cache memory, a delicate wiring on the printed circuit board has influence on the characteristic of the operation. If the printed circuit board on which the MPU is mounted is limited, it is not necessary to excessively reserve an operational margin of the LSI.
The secondary cache memory of the MPU for the large computer is mounted on the module, as mentioned above. Thus, the restriction on the printed circuit board and LSI assembling technique imposes a limit on a bus width between the MPU and the secondary cache memory.
On the other hand, expansion of the bus width enables the performance to be improved. Hence, it may be considered that DRAM (Dynamic Random Access Memory) having a large memory capacity per unit area is used as the secondary cache memory.
As in the conventional case, if the SRAM is mounted in the MPU module as the secondary cache memory, the wirings between the SRAM and the MPU are installed to make their lengths as similar as possible to each other. Therefore, the wiring delay times are uniform with each other, and the operation margin of the LSI can be observed widely. The MPU and the SRAM are the main elements on the module, and the size of the printed circuit board does not have substantial influence on the cost of the module. Thus, it is easy to uniformly arrange the wiring lengths between the SRAM and the MPU.
On the contrary, a problem when the DRAM is mounted on the same chip as the MPU as the secondary cache memory is that an access time of the DRAM is typically slower than that of the SRAM. As a countermeasure against this problem, the DRAM is divided into a plurality of sections. The memory cell array and the peripheral circuit portion of the DRAM are divided into the plurality of sections, respectively.
Accordingly, a wiring delay in an access path of the DRAM is reduced to thereby attain an access time similar to that of the SRAM. In addition, an access time from the MPU to the cache memory is determined by the MPU. It corresponds to the two clocks in the MPU used in a later-described embodiment. That is, a cycle time of a clock can be shorten by shortening an access time of the DRAM. However, it is still insufficient. As mentioned above, both the memory cell array and the peripheral circuit portion of the DRAM are minutely divided. Thus, there are many address input ports in the DRAM, as compared with a case when the SRAM is used on the MPU module.
However, the size of the chip has large influence on the cost. Thus, each position of the DRAM macros is optimized so as to reduce the chip size to a minimum. Hence, in order to uniform the delay times of signal transmitted from the MPU to the DRAM macros, it is not allowable to optimize the positions of the DRAM macros.
Japanese Laid Open Patent Application (JP-A-Heisei 7-141869) discloses a technique in which the number of selection transistors 11 is small, and a rising speed of a signal is fast, and a row selection line selection signal to output a data of a memory cell faster than a latch signal from an ATD (Address Transition Detector) circuit 7 is delayed by an addition of a delay circuit.
Japanese Laid Open Patent Application (JP-A-Heisei 10-256512) discloses a technique for realizing a high speed by intensively mounting an address buffer and a bonding pad for an address input and thereby shortening a length of a wiring to transmit an address signal line.
However, the above-mentioned two techniques can not make the cycle time shorter, if the DRAM macro and the MPU are mounted on the same chip as in the present invention.
The present invention is accomplished in view of the above mentioned circumstances. Therefore, an object of the present invention is to provide a semiconductor device in which MPU and DRAM as a secondary cache memory are mounted on the same chip so as to easily realize a high speed of a cycle time under a restriction on a chip size.
In order to achieve an aspect of the present invention, a semiconductor device includes an MPU (Micro Processing Unit) section provided on a chip to output a clock signal and an address signal, a DRAM (Dynamic Random Access Memory) section provided on the chip to input the clock signal and the address signal, a plurality of address registers, wherein each of the plurality of address registers latches the address signal in response to the clock signal, and a plurality of address delay compensating units, wherein each of the plurality of address delay compensating units is provided in a previous stage to the plurality of address registers and compensates for an address signal transmission delay time such that the address signal transmission delay time falls within a predetermined range, the address signal transmission delay time indicating a time elapsed before the each address register inputs the address signal after the MPU section outputs the address signal.
In order to achieve another aspect of the present invention, a semiconductor device includes an MPU (Micro Processing Unit) section provided on a chip to output a clock signal and a plurality of address signals a plurality of DRAM (Dynamic Random Access Memory) sections, wherein each of the plurality of DRAM sections is provided on the chip and inputs the clock signal and one of the plurality of address signals a plurality of address registers provided in each of the plurality of DRAM sections wherein each of the plurality of address registers latches the one of the plurality of address signals in response to the clock signal and a plurality of address delay compensating units, wherein each of the plurality of address delay compensating units is provided in a previous stage to the plurality of address registers and compensates for an address signal transmission delay time such that the address signal transmission delay time falls within a predetermined range, the address signal transmission delay time indicating a time elapsed before the each address register inputs the address signal after the MPU section outputs the address signal.
In this case, each of the plurality of address delay compensating units includes a plurality of buffers, and the address signal transmission delay time is compensated such that the address signal transmission delay time falls within the predetermined range, based on a number of the buffers.
Also in this case, each of the plurality of address delay compensating units includes a buffer, and the address signal transmission delay time is compensated such that the address signal transmission delay time falls within the predetermined range, based on a transistor size of the buffer.
In order to achieve still another aspect of the present invention, a semiconductor device further includes a clock signal phase adjusting unit provided in another previous stage to the plurality of address registers to match phases of the clock signals respectively inputted to the plurality of address registers with each other.
In this case, the clock signal phase adjusting unit includes a first stage buffer inputting the clock signal outputted from the MPU section and a plurality of second stage buffers which are branched in parallel to each other from an output section of the first stage buffer, and the clock signal outputted through the first stage buffer and at least one of the plurality of second stage buffers is supplied to each of the plurality of address registers.
Also in this case, a semiconductor device further includes a clock signal phase shifter shifting in leading direction a phase of the clock signal generated in the MPU section to output from the MPU section.
Further in this case, a semiconductor device further includes a clock signal phase adjusting unit provided in another previous stage to the plurality of address registers to match phases of the clock signals respectively inputted to the plurality of address registers with each other and a clock signal phase shifter shifting in leading direction a phase of the clock signal generated in the MPU section to output from the MPU section, and wherein the clock signal phase shifter performs a feedback control based on the clock signal after passing through the clock signal phase adjusting unit.
In this case, respective address signal output sections of the plurality of address delay compensating units are connected to each other.
Also in this case, the DRAM section functions as a secondary cache memory of the MPU section.
Further in this case, the MPU section is provided in a substantial center position on the chip, two of the plurality of DRAM sections are respectively provided in left and right sides of the MPU section on the chip, as a secondary cache memory of the MPU section and one of the plurality of DRAM sections other than the two DRAM sections is provided on one of top and bottom sides of the MPU section on the chip, as a tag (TAG) section of the MPU section.
In order to achieve yet still another aspect of the present invention, a semiconductor device includes an MPU (Micro Processing Unit) section provided on a chip to output a clock signal and to input and output a data signal, a DRAM (Dynamic Random Access Memory) section provided on the chip to input the clock signal and to input and output the data signal, a plurality of data-in registers, wherein each of the plurality of data-in registers latches the inputted data signal in response to the clock signal, a plurality of data-out registers, wherein each of the plurality of data-out registers latches the data signal in response to the clock signal and a plurality of data-in delay compensating units, wherein each of the plurality of data-in delay compensating units is provided in a previous stage to the plurality of data-in registers and compensates for a data signal transmission delay time such that the data signal transmission delay time falls within a predetermined range, the data signal transmission delay time indicating a time elapsed before the each data-in register inputs the data signal after the MPU section outputs the data signal.
In this case, a semiconductor device further includes a switching unit provided between the plurality of data-in delay compensating units and the plurality of data-out registers, wherein the switching unit switches between a state in which the data signal is inputted to the each data-in register and another state in which the data signal is outputted from the each data-out register.
In order to achieve another aspect of the present invention, a semiconductor device includes an MPU (Micro Processing Unit) section provided on a chip to output a clock signal and an address signal and to input and output a data signal, a DRAM (Dynamic Random Access Memory) section provided on the chip to input the clock signal and the address signal and to input and output the data signal, a plurality of address registers, wherein each of the plurality of address registers latches the address signal in response to the clock signal, a plurality of data-in registers, wherein each of the plurality of data-in registers latches the inputted data signal in response to the clock signal, a plurality of data-out registers, wherein each of the plurality of data-out registers latches the data signal in response to the clock signal, a plurality of address delay compensating units, wherein each of the plurality of address delay compensating units is provided in a previous stage to the plurality of address registers and compensates for an address signal transmission delay time such that the address signal transmission delay time falls within a predetermined range, the address signal transmission delay time indicating a time elapsed before the each address register inputs the address signal after the MPU section outputs the address signal and a plurality of data-in delay compensating units, wherein each of the plurality of data-in delay compensating units is provided in a previous stage to the plurality of data-in registers and compensates for a data signal transmission delay time such that the data signal transmission delay time falls within a given range, the data signal transmission delay time indicating a time elapsed before the each data-in register inputs the data signal after the MPU section outputs the data signal.
In order to achieve another aspect of the present invention, a semiconductor device includes an MPU (Micro Processing Unit) section provided on a chip to output a clock signal and a plurality of address signals and to input and output a plurality of data signals, a plurality of DRAM (Dynamic Random Access Memory) sections, wherein each of the plurality of DRAM sections is provided on the chip and inputs the clock signal and one of the plurality of address signals and inputs and outputs one of the plurality of data signals, a plurality of address registers provided in each of the plurality of DRAM sections wherein each of the plurality of address registers latches the one of the plurality of address signals in response to the clock signal, a plurality of data-in registers provided in each of the plurality of DRAM sections wherein each of the plurality of data-in registers latches the one of the plurality of data signals in response to the clock signal, a plurality of data-out registers provided in each of the plurality of DRAM sections wherein each of the plurality of data-out registers latches the one of the plurality of the data signals in response to the clock signal, a plurality of address delay compensating units, wherein each of the plurality of address delay compensating units is provided in a previous stage to the plurality of address registers and compensates for an address signal transmission delay time such that the address signal transmission delay time falls within a predetermined range, the address signal transmission delay time indicating a time elapsed before the each address register inputs the address signal after the MPU section outputs the address signal and a plurality of data-in delay compensating units, wherein each of the plurality of data-in delay compensating units is provided in a previous stage to the plurality of data-in registers and compensates for a data signal transmission delay time such that the data signal transmission delay time falls within a given range, the data signal transmission delay time indicating a time elapsed before the each data-in register inputs the data signal after the MPU section outputs the data signal.
In this case, a semiconductor device further includes a switching unit provided between the plurality of data-in delay compensating units and the plurality of data-out registers, wherein the switching unit switches between a state in which the data signal is inputted to the each data-in register and another state in which the data signal is outputted from the each data-out register.
Also in this case, each of the plurality of address delay compensating units and each of the plurality of data-in delay compensating units respectively include a plurality of buffers, and the address signal transmission delay time and the data signal transmission delay time respectively are compensated such that the address signal transmission delay time and the data signal transmission delay time fall within the predetermined range and the given range, based on a number of the buffers.
Further in this case, each of the plurality of address delay compensating units and each of the plurality of data-in delay compensating units respectively include a buffer, and the address signal transmission delay time and the data signal transmission delay time respectively are compensated such that the address signal transmission delay time and the data signal transmission delay time fall within the predetermined range and the given range, based on a transistor size of the buffers.
In this case, a semiconductor device further includes a clock signal phase adjusting unit provided in another previous stage to the plurality of address registers to match phases of the clock signals respectively inputted to the plurality of address registers with each other.
Also in this case, the clock signal phase adjusting unit includes a first stage buffer inputting the clock signal outputted from the MPU section and a plurality of second stage buffers which are branched in parallel to each other from an output section of the first stage buffer, and the clock signal outputted through the first stage buffer and at least one of the plurality of second stage buffers is supplied to each of the plurality of address registers.
Further in this case, a semiconductor device further includes a clock signal phase shifter shifting in leading direction a phase of the clock signal generated in the MPU section to output from the MPU section.
In this case, a semiconductor device further includes a clock signal phase adjusting unit provided in another previous stage to the plurality of address registers to match phases of the clock signals respectively inputted to the plurality of address registers with each other and a clock signal phase shifter shifting in leading direction a phase of the clock signal generated in the MPU section to output from the MPU section, and wherein the clock signal phase shifter performs a feedback control based on the clock signal after passing through the clock signal phase adjusting unit.
Also in this case, respective address signal output sections of the plurality of address delay compensating units are connected to each other.
Further in this case, the DRAM section functions as a secondary cache memory of the MPU section.
In this case, the MPU section is provided in a substantial center position on the chip, two of the plurality of DRAM sections are respectively provided in left and right sides of the MPU section on the chip, as a secondary cache memory of the MPU section and one of the plurality of DRAM sections other than the two DRAM sections is provided on one of top and bottom sides of the MPU section on the chip, as a tag (TAG) section of the MPU section.